ATM Circuit Emulation with Asynchronous Clocks and Random Clock Frequencies

Kerry W. Fendick (AT&T)

Sanjay Mithal (Lucent Technologies)*

Luis E. Morales (AT&T)

Sources of Constant Bit Rate (CBR) traffic on Asynchronous Transfer Mode (ATM) connections typically generate ATM cells at fixed intervals determined by the frequency of an internal clock. Statistical multiplexers of such sources are commonly modeled as queues that serve a superposition of periodic arrivals with random phases. We call this the "random phase model." For this model, the steady-state queue- length distribution has the interpretation of an average over the ensemble of such queues, but not necessarily over the realization of any given queue. Indeed, in the special case where all sources have the same period, the queue-length process for any given queue is itself periodic, and cells arriving from any one source after the first period always see the same queue length. Nevertheless, the queue-length distribution for the ensemble is commonly used to describe the variation of delays of cells from a single source. In this talk, we describe conditions under which this heuristic makes sense. In particular, we describe how small, inevitable differences in clock frequencies result in variations in delays at any given queue, and we describe relationships between the random phase model and this "random frequency model". In the process, we present some ergodic theorems for CBR queues.

*This work was done while Sanjay Mithal was with AT&T.