- Start Date:
July 5, 2017
- Event Start Time:
2:00 PM
- Event End Time:
3:00 PM
- Organizers:
Lazaros Gallos
- Seminar Series:
REU Seminar
- Presenter(s):
Caroline Trippel - Princeton University
- Event Location:
DIMACS Seminar room
- Abstract:
Computer architecture is a mediator between technology and applications. It is what enables us to separate interface (i.e., the specification of what services and functionality technology must provide) from the technology itself. For many years, advances in transistor technology enabled an exponential increase of the number of transistors on a computer chip. This resulted in increased single-core processor speeds with little innovation needed in overall chip design. In order to achieve continued performance scaling at manageable power and thermal levels, modern computer systems employ increasing amounts of parallelism and heterogeneity/specialization. For example, the hardware in a smartphone does not just include general purpose processors, but also specialized accelerators (e.g. for encryption or image processing) and/or on-chip microcontrollers. These heterogeneous and parallel systems generally operate under the abstraction of a shared, unified, address space, i.e., shared memory. The combination of parallelism and shared memory necessitates memory consistency models which specify the rules and guarantees about the ordering and visibility of accesses to shared memory. In this talk, I will give some motivation for the existence of memory consistency models, explain our work on memory consistency model verification both below the hardware-software interface and across the hardware software stack, and summarize with the importance of continued work in this area.
