« Modular Bosonic Quantum Computing with Multimode Circuit QED
May 16, 2025, 5:10 PM - 5:30 PM
Location:
DIMACS Center
Rutgers University
CoRE Building
96 Frelinghuysen Road
Piscataway, NJ 08854
Click here for map.
Srivatsan Chakram, Rutgers University
Circuit quantum electrodynamics (cQED) with superconducting cavities coupled to nonlinear elements such as transmons offers a powerful platform for quantum information processing, combining long cavity coherence times with the benefits of bosonic error correction. Multimode cQED architectures further enhance hardware efficiency and connectivity, enabling gate operations between arbitrary pairs of cavity modes using only a few control lines.
However, these systems face key challenges, including ancilla-induced crosstalk and decoherence, as well as cavity errors from ancilla backaction and the inverse Purcell effect—issues that become more pronounced as cavity coherence improves.
In this talk, I will present recent experimental implementations of strategies to mitigate ancilla-induced errors by weakening dispersive coupling while preserving fast gate speeds through ancilla displacements. Using sideband drives, we realize a tunable Jaynes–Cummings interaction between a transmon and any cavity mode, enabling SWAP gates nearly 40× faster than those in the bare dispersive regime. Building on this capability, we demonstrate fast multimode state preparation using only transmon rotations and sideband SWAPs via a novel state-shelving protocol. This approach enables the preparation of Fock, superposition, and binomial code states across ten cavity modes, as well as unitaries that encode transmon superpositions into entangled NOON states between arbitrary mode pairs.
By leveraging residual dispersive interactions to synchronize sideband transitions across photon numbers, we further implement a broader class of unitaries—including a new binomial encoding unitary with gate speeds approaching the bare dispersive shift. I will conclude with a preview of next-generation multimode processor designs aimed at mitigating inter-mode crosstalk and ancilla faults at the hardware level.